1. Field of the Invention
This application relates to semiconductor design process and, particularly, to integrated circuit (IC) design process including electronic design automation (EDA) and automated IC design tools.
2. Background Art
Modem IC design process depends on a highly developed software technology directed to optimizing IC density, timing, and other electrical parameters in order to achieve low cost, improved performance, and high reliability while reducing overall design turn-around-time. It is common to find computer-aided IC design tools (also known as CAD tools and EDA tools, hereafter collectively xe2x80x9cIC design toolsxe2x80x9d) that are utilized for the design of complex ICs with millions of components. To deal with such complexity, IC design tools must have the capacity to process millions of gates, must be computationally fast, and must produce optimal results in order to reduce the number of iterations in the design flow (See FIG. 1 for a typical IC design flow). In other words, IC design tools must keep pace with the rapidly increasing complexity as outlined by Moore""s Law. (Moore""s Law predicted that the design complexity and speed of ICs will double every two (2) years; See FIG. 2 for a Semiconductor Industry Association""s (SIA""s) projection of IC complexity development along with the increased importance of deep-submicron (DSM) for physical design.
Over time there have been many generations of IC design tools for handling the increasing number of components (e.g., gates) on a single chip. The increasing IC complexity overtime resulted in the evolution of IC design methods including adoption of higher levels of abstraction as illustrated in FIG. 3. FIG. 3, shows the evolution over time of ICs, from small ICs comprised of transistors (or polygons) to larger ICs comprised of higher levels of abstraction such as gates, (or cells), and blocks.
Early on, with a relatively small number of gates, logic design with transistors and physical design with polygons 30 in an IC 40 was performed manually. With the emergence of synthesis and placement and routing (PandR) tools, gates and standard cells 32 have been introduced as a basic architectural feature for the design and implementation of ICs. As a result, the physical design and implementation of ICs was automated using the standard-cell-based architecture 42. Physical design tools, particularly, automated physical design tools, have long been key in implementing the IC design evolution. In general, physical design of an IC is the process of converting electrical circuit specifications into an IC layout. Physical design requires exacting details about components, geometric patterns and geometric rules, such as separation, spacing, etc. Physical design automation tools use algorithms and data structures to achieve optimal arrangement of components and efficient interconnection between components to obtain the desired functionality. However, unlike front-end design tools (e.g., logic design tools), physical design tools have not kept pace with the IC evolution. Physical design tools for both flat standard-cell-based and functional-block-based architectures 42 and 44 are inadequate and have not kept pace with large scale ICs design. For example, automatic PandR tools for implementing ICs with a flat cell-based architecture 42 are reaching practical limits in the number of cells they can process automatically; and PandR tools for implementing ICs with a functional block-based architecture 44 are less automatic thus consuming more designer resources.
The development of functional block-based architecture 44, came into existence with the evolution of synthesis tools that gave rise to Register Transfer Level (RTL) design. RTL was introduced to specify the IC functionality design with a behavior-level specification. Behavioral and RTL specifications can be coded in any currently available hardware description language (HDL). From RTL, gate level information can be generated by logic synthesis tools, and this information (commonly referred to as the xe2x80x9cnetlistxe2x80x9d) can be used in generating layout including physical interconnections (wires) between the gates (which are provided as part of the netlist). The transition from gate-level to RTL-level methodologies in the front-end design tools accommodates the evolution of IC design, but the limitations in the back-end (e.g. physical) design tools have yet to be overcome. To better understand these limitations, an overview of the standard-cell-based and functional-block-based architectures and corresponding design methodologies are illustrated in FIGS. 4 and 5, respectively.
As shown in FIG. 4, standard cell architecture of an IC 42 considers the IC layout to be formed of rectangular cells 54 with a similar height, the so-called standard cells. The standard cell layout is inherently non-hierarchical, hence the term flat cell-based design. In this layout, cells 54 are placed in rows 52 with, or without, spaces (channels) therebetween. In a layout with channels (not shown), the channels are used to accommodate wires for cell interconnections. In a layout without channels, all interconnections are routed over the cells. In the standard-cell-based architecture 42, each cell 54 is equivalent to a primitive component of the circuit embodied in the IC. The functionality of each cell is typically predefined and available from a cell library. After the logical design phase 14 (e.g., by high-level synthesis from behavioral description to RTL code followed by RTL synthesis to gate-level), the design process proceeds with the physical design phase 16. The standard cell design style is relatively simple but has practical limitations for processing large ICs, primarily due to the fact that physical design deals with significantly more design elements than logic design. Also, long interconnects in large-scale standard cell layout typically leads to non-deterministic timing results or signal integrity issues. As a result, standard cell design optimization requires a repeat in a number of iterations of either one or both of the logical and physical design phases 14 and 16 (indicated by return arrows). For instance, engineering design change orders (ECOs) which introduce changes in the design (e.g., function, netlist, or timing) require a repeat of the standard cell design cycle. Moreover, although a cell-based approach is fairly automatic, substantial efforts and resources must be expended in large scale IC designs to maintain synchronization between the vast information generated, respectively, by the logical and physical design teams.
By comparison, in an IC with a functional block-based design architecture 44, as shown in FIG. 5, the circuit embodied in the IC is partitioned (step 11) into a hierarchy of functional blocks 62. Each individual functional block can be implemented by being further partitioned into a hierarchy of sub-blocks, or by using a standard cell approach as described above. Each IC design team is typically responsible for the logical and physical design of a respective functional block. However, as the individual block designs progress there remains a challenge to synchronize tuning of the design requirements and related information among the individual design teams. A separate top-level design team must then assemble the functional blocks in an integration phase performed at a top-level of the hierarchy using floor planning (or chip assembly) tools. Reconciling mismatches between the functional blocks requires ECOs and is a significant challenge which floor planning tools cannot easily overcome with predictable results.
The difficulties associated with a functional block design style are due to the irregular sizes and diverse timing requirements of functional blocks 62. Because the floor planning involves a multiple number of constraints (such as overall IC and blocks size, aspect ratio, timing, pin accessibility, etc.), optimizing the design with functional blocks, particularly with PandR tools, is far more complex and requires a number of design iterations (See FIG. 5: return arrows). Also, due to the wide range of functional block sizes some phases of the physical design (such as floorplan optimization) are performed manually in a time consuming process (hence, the semi-automatic physical design).
As the complexity of IC circuits evolves to include entire systems on a single chip (SOC), the number of functional blocks in the IC increases and their respective design styles of these blocks diverge. For example, SOC design increasingly includes functional blocks, which are provided in two forms, soft IP and hard IP. Soft IP is provided in RTL (or gate level netlist) form which provides design flexibility and process independence. However, soft IP requires the additional process of conversion into hard IP (i.e., the physical design implementation) before manufacturing the chip. Hard IP is provided in ready to use layout form (or placed and routed standard cells), but it is inflexible (or rigid as explained before) and difficult to adapt into a new manufacturing process. Hard IP may be comprised only of standard cells or a combination of standard cells and/or custom circuitry such as analog blocks, memory blocks, and processor blocks. As the number of design blocks and styles increases, the complexity of placement, routing, timing, and signal integrity optimization increases as well. With the irregular nature of functional blocks, a change at any level of the hierarchy (even inside a functional block) effects the entire design and complicates ECOs. Furthermore, the irregular size of the functional blocks compounds the difficulty to optimize placement, minimize timing, increase density, and minimize the length of interconnections between the blocks.
Achieving IC performance objectives in large scale IC design implementations with the soft and/or hard IP blocks presents difficult chip assembly challenges. Particularly difficult is the timing closure during physical layout implementation 16. Further design optimization after completion of the synthesis and physical layout phases is often needed to meet performance objectives such as timing, signal integrity, power and noise immunity. Design optimization requires a return to the synthesis phase 14, or floor planing phase 11, in order to consider parasitic electronic parameters (i.e., resistor capacitor, RC, data and delay values). Namely, design optimization involves iterative loops (indicated by the return arrows) that make it difficult to converge on a solution that closely meets the design specifications and objectives. This, of course, leads to design flow bottlenecks and delays in design completion. The problem is compounded as conventional IC design tools ignore RTL hierarchy, which complicates passing back of information to the RTL stage.
Accordingly, for the increasingly complex large scale ICs it is increasingly difficult to achieve the desired low cost, fast turn-around-time, high yield, high performance and reliability. Therefore, there remains a need to improve IC design methods and tools.
The present invention addresses the foregoing and related problems by allowing acceleration of the integrated circuit (IC) design process while optimizing critical IC design parameters such as density, timing, and reliability. Specifically, the present invention introduces an IC architecture with STANDARD BLOCKs that substantially improves complex, large scale, deep-submicron high speed IC designs. (As mentioned later in the detailed description of the invention, STANDARD BLOCK and STANDARD BLOCK ARRAY are trademarks of Ammocore Technology, Inc., the assignee of the present invention.)
In the new IC architecture, the STANDARD BLOCKs provide a new standard platform for physical design that substantially reduces the complexity associated with large scale, deep-submicron high speed IC design, such as the SOC (system on chip) design. The new IC architecture is created with STANDARD BLOCKs having a STANDARD BLOCK architecture. The STANDARD BLOCK architecture introduces STANDARD BLOCKS as a new level of abstraction which is higher than standard cells, and their relative size is, on average, smaller than functional blocks"" size. STANDARD BLOCKs are physical representations of portions of a logic netlist.
The new IC architecture, contains a plurality of STANDARD BLOCKs arranged in a channeled or channel-less STANDARD BLOCK ARRAYs. Furthermore, each STANDARD BLOCK contains a plurality of standard cells arranged in a channeled or channel-less cell-based array configuration. For the purpose of simplified and more efficient top-level assembly, as will later become clear from the description herein, the number of cells in each STANDARD BLOCK is designed to be large enough to simplify top-level timing analysis (with less complex timing abstractions), yet small enough to simplify top-level placement and maximize IC density. As further compared to standard cells, STANDARD BLOCKs have more properties than standard cells. Consistently, STANDARD BLOCKs have both functional and physical properties such as timing, power, size, number of cells (or pins), etc. In other words, STANDARD BLOCKs are entities in which these properties and characteristics are consistently present.
By providing the STANDARD BLOCKs as a physical representation at a higher abstraction level than standard cells and by eliminating the irregularity associated with functional blocks, the new IC architecture enables increased IC layout density, improved timing, and higher reliability. In so doing, an IC implementation with the STANDARD BLOCK architecture combines the advantages of standard-cell-based and functional-block-based architectures.
With the new IC architecture, STANDARD BLOCKs in the IC architecture have a physically constrained xe2x80x9cformxe2x80x9d yet flexible physical design properties. For the purpose of this application, the xe2x80x9cformxe2x80x9d of a STANDARD BLOCK is a surface area defined or occupied by a STANDARD BLOCK which preferably approximates, but is not limited to, a rectangular-shaped area. The xe2x80x9cphysically constrainedxe2x80x9d form is, in turn, a shape the dimensions of which are constrained but capable of being scalable relative to IC size and process technology.
Being physically constrained, the form of STANDARD BLOCKs is characterized by one fixed or quantized dimension and one xe2x80x9cvariable xe2x80x9d dimension that is selectable between predefined limits. Namely, STANDARD BLOCKs preferably have a similarly fixed or quantized height and variable widths or, alternatively, variable heights and a similarly fixed or quantized width. The height and width dimensions of each STANDARD BLOCK are preferably expressed in terms of number of minimal-size cells (i.e., the smallest cells available in the design library).
The new IC architecture is advantageously implemented with STANDARD BLOCK ARRAYs, each containing a plurality of STANDARD BLOCKs arranged in a row or column configuration. STANDARD BLOCKs are placed adjacent to each other with their fixed or quantized dimension aligning one another, such that each STANDARD BLOCK ARRAY is contiguous. Individual STANDARD BLOCK ARRAYS, are placed in either channel-less or channeled configuration with respect to one-another. In a channel-less STANDARD BLOCK ARRAY configuration the individual row or column based arrays are flipped in an alternate fashion and placed next to each other such that their respective VDD (power) and GND (ground) can be shared between the rows or columns. In a channeled STANDARD BLOCK ARRAY configuration, the individual rows or columns are spaced apart forming channels between the arrays of STANDARD BLOCKs which can be used to accommodate interconnect resources. The number of STANDARD BLOCK ARRAYs is determined by the dimensions of the IC and the dimensions of the STANDARD BLOCKs. The dimensions of STANDARD BLOCKs range from a pre-defined minimum to a maximum number of cells and pins.
The new IC architecture further includes a plurality of standard cells at the top level. These top-level cells are intermixed with the STANDARD BLOCKs by being placed in reserved sites around the perimeter or inside the STANDARD BLOCKs, or in reserved channels between STANDARD BLOCK ARRAYs. Top-level cells are typically buffers, repeaters and other glue logic, and are typically utilized in a global context, such as splitting long interconnects, implementing clock trees, and accommodating functions such as control logic and test-scan. As such, the new IC architecture includes a plurality of STANDARD BLOCKs, top-level cells, and IP (intellectual property) in a single IC.
The new IC architecture further includes power grid and clock grid structures providing, respectively, power and ground and clock distribution to the STANDARD BLOCKs and the top-level cells. The power structure for the IC is implemented by abutting STANDARD BLOCKs containing special power grid structure, and filling any unused space with special power routing, or special filler STANDARD BLOCKs.
To implement the new IC architecture, STANDARD BLOCKs are created by partitioning a full hierarchical RTL (register transfer level) design or a structural netlist of the IC (or IP part thereof) into smaller functional modules, thereby adopting the advantages of functional block architecture without assuming its shortcomings. Because of the regularity and granularity of the STANDARD BLOCKs, which facilitates the formation of STANDARD BLOCK ARRAYs, the implementation of STANDARD BLOCK based IC design can be realized with conventional placement tools.
A STANDARD BLOCK or a collection of STANDARD BLOCKs introduces an abstraction that, preferably but not invariably, aligns to the RTL functional block boundaries, or RTL sub-block boundaries. Since one or more STANDARD BLOCKs correspond to the RTL functionality, STANDARD BLOCKs corresponding to various modules of intellectual property (soft IP or hard IP, as mentioned above) can, in turn, be created for easy re-use in other designs (with minimal or no additional changes to the STANDARD BLOCKs). The alignment of STANDARD BLOCKs to the RTL functionality also provides a common platform for both the RTL design and the physical design. This makes passing information back to the RTL level much easier (for performing a re-design, for example, in order to meet physical constraints).
For the purpose of top-level assembly for forming the IC, the STANDARD BLOCKs are provided as a general physical abstraction such that each STANDARD BLOCK is akin to black box model with the majority of its internal design aspects being invisible to a top-level assembly tool while selected aspects of its internal design remain visible. Each STANDARD BLOCK can be presented to the assembly phase in terms of its respective fundamental properties as well as its respective characteristics which take the form of abstractions. Namely, each of the STANDARD BLOCKs can be uniquely characterized by its fundamental properties and characteristics such as, size, number of gates, number of I/O pins, clock, power, and timing, and by using various abstractions which model physical block placement, interconnects, etc.
Thus, in accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a new IC architecture with STANDARD BLOCKs. The features of STANDARD BLOCKs in the IC architecture are defined by the STANDARD BLOCK architecture and are provided thereby as a new level of abstraction. The new level of abstraction has a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs. To this end, as noted above, the new IC architecture combines the advantages of standard-cell-based and functional-block-based architectures.
As further noted above, the STANDARD BLOCKs are invariably provided in the new IC architecture with a form that is physically constrained. This form has one fixed or quantized dimension and one variable dimension that ranges between predefined limits. The STANDARD BLOCKs have a granularity and a level of abstraction that are larger and higher, respectively, than a standard cell granularity and level of abstraction such that each standard block includes a plurality of standard cells. The STANDARD BLOCKs additionally have the above-mentioned flexible physical design properties. The layout of the new IC is implemented with STANDARD BLOCKs arranged in a STANDARD BLOCK ARRAY configuration, and with top-level cells positioned in a configuration that is suited to meet timing and signal integrity for the IC.
Various modifications to the preferred embodiment will be apparent to those skilled in the art from consideration of the disclosure and practice of the invention disclosed herein and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with principles and features described herein.
Furthermore, advantages of the invention will be understood by those skilled in the art from the description that follows. Advantages of the invention will be further realized and attained from practice of the invention disclosed herein.